The Institute of Microelectronics (IME) has formed a consortium with various private semiconductor companies to research copper wire bonding issues related to corrosion and stress.
The IME, an entity under the Singapore government's Agency for Science, Technology and Research (A*STAR), announced the Copper (Cu) Wire Bonding Consortium II. The objective of this initiative is to improve the reliability of semiconductor devices.
The Phase I was established in 2010 and concentrated on developing microsensor-based methodology to measure the wire bonding stress and perform reliability characterisation of wire bonds.
Members of the Consortium II span across the semiconductor supply chain including Atotech S.E.A., GLOBALFOUNDRIES, Heraeus Materials and Infineon Technologies.
"IME has been dominant in the R&D of advanced packaging technologies and remains focused on developing solutions to help the industry reduce manufacturing costs," said Prof. Dim-Lee Kwong, executive director of IME. "We are excited to begin a new phase of the Cu Wire Bonding Consortium to enable the development of robust, high reliability and low cost interconnection solutions."
Copper, which offers favourable cost, performance, quality and reliability benefits over gold, has become one of the preferred materials for wire bonding interconnects in microelectronics. Today, however, the industry still faces many technical challenges in developing copper as the best choice for chip-to-package interconnection.
One of the key technical issues is related to copper's hardness relative to gold, which requires bonding parameters to be very well controlled in order to eliminate the risk of damaging bond pads and underlying structures. Another daunting challenge of using copper is its reactivity with oxygen in the surrounding air which causes corrosion-related problems. These two issues can affect the reliability and quality of semiconductor devices.
The IME Cu Wire Bonding Consortium II will conduct a study on corrosion and the mechanisms on the effect of various packaging materials. To understand the effects of copper wire hardness when bonding on different materials, the consortium will carry out modelling and characterisation of copper wire bonding stress using stress sensors developed under the scope of Phase I to provide an improved technique of measuring wire bonding stress. The outcome of this work will enable semiconductor manufacturers as well as test and packaging houses to develop solutions to improve product reliability, especially those targeted at high reliability applications.
"GLOBALFOUNDRIES is pleased to be in this consortium as the first phase of our partnership has successfully resulted in optimising 0.7 mil in copper wire bonding on our 40nm product and passed the JEDEC reliability test," commented K. C. Ang, senior vice president and general manager for GLOBALFOUNDRIES Singapore. "The success has brought us to the next phase of collaboration where the process will be tested on our advanced 28nm product."
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