For example, Handy said, instead of having multiple DIMMS (which can range from one to four) on a motherboard, you would need only one Hybrid Memory Cube, cutting down on the number of interfaces to the CPU.
The HMC has defined two physical interfaces back to a host system processor: a short reach and an ultra-short reach. The short reach is similar to most motherboard technologies today where the DRAM is within eight to 10 inches of the CPU. That technology is aimed mainly for use in network applications and has the goal of boosting throughput from as much as 15Gbps to 28Gbps per lane in a four-lane configuration.
"The first package we're going to launch commercially in the second half of this year is in a fairly large package because fundamentally the networking base doesn't want package pitch lower than 1 millimeter on the ball pitch for the bottom of the ball grid array," Black said. "So physically the logic chip and the DRAM die are in the 100 square-millimeter size sitting on a bigger package to accommodate the ball-out requirements for a short reach design in a networking platform."
The ultra short-reach interconnection definition is focused on a low energy, close-proximity memory design support of FPGAs, ASICs and ASSPs, such as high-performance networking, and test and measurement applications. That will have a one to three-inch channel back to the CPU, and it has the throughput goal of 15Gbps per lane.
"It's optimized at very low energy signaling for multi-chip modules," Black said. "That's where you'll see a very small package form factor where you're sub-300 micron ball pitch."
While 3D DRAM will cost more to make than its predecessor, Black pointed out that it would cost more to gain the aggregate bandwidth using standard DRAM modules.
"If you look at the total cost of offering a cube, versus trying to get to that kind of bandwidth with traditional DRAM technology, we can in many cases show the total system cost as being much better with Hybrid Memory Cube," he said."
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